Advances in semiconductor chip fabrication and packaging technologies has enabled development of highly integrated semiconductor chip devices and compact chip package structures (or electronic modules). As chip geometries are scaled down and operating speeds are increased and chip packages become more compact, however, power densities are increased resulting in more heat generation per unit area. Indeed, heat is primarily generated from wiring resistance and active device switching. The ability to implement electronic modules with increased chip densities and system performance is limited primarily by the ability to effectively remove heat from such electronic modules as resulting increased heat densities makes packaging more problematic. Indeed, substantial stresses and strains may be generated in a package structure caused by thermal cycling during chip operation, leading to device failure and structural defects.
More specifically, by way of example, an electronic module may comprise one or more semiconductor chips that are electrically and mechanically coupled to a substrate (or chip carrier) by soldering conductive contacts on the chip (e.g., C4 (Controlled Collapse Chip Connection) solder balls) to the top surface of the substrate. Moreover, an electronic module may comprise two or more levels of substrates that enable different levels of space transformation of an electrical interface to the chips. When the chips and substrates are formed from different materials having different coefficients of thermal expansion (CTE), the chip and substrate tend to expand and contract by different amounts during thermal cycling, which is a phenomenon known as “CTE mismatch”. The CTE represents the ratio of change in dimensions to original dimensions per degree rise in temperature, expressed in ppm/° C. CTE mismatch denotes the difference in the coefficients of thermal expansions of two materials or components joined together, which produces strains and stresses at joining interfaces or in attachment surfaces.
During thermal cycling, relative displacement between components due to differences in CTE between such components can cause bowing or bending of substrates and generate significant stresses and strains in the electrical contacts and interface between the components. For instance, relative displacement between a chip and a carrier substrate and/or between two substrates (e.g., carrier and printed wiring board (PWB) or printed circuit board PCB) due to thermal cycling can deform the electrical interconnections between the components. These stresses are applied repeatedly with repeated operation of the device, and can cause fatigue of the electrical interconnections, especially C4s.
FIG. 1 is a schematic side-view of a conventional chip package (100). The package (100) comprises a semiconductor IC chip (101) mounted on a carrier substrate (102). The IC chip (101) is shown flip-chip bonded to bond sites on the carrier substrate (102) using an array of fine pitch solder balls (103) such as micro C4 (Controlled Collapsed Chip Connect) solder balls, which provide electrical connections between I/O pads on the active surface of the chip (101) and a footprint of corresponding pads on the surface of the chip carrier (102). The chip (101) may be formed on silicon and the carrier substrate (102) formed of ceramic or silicon. The interconnect between chip (101) and carrier substrate (102) may be strengthened with the addition of an underfill.
The chip carrier substrate (102) is electrically coupled to an organic substrate (104) using an array of larger pitch solder balls (105) (e.g., C4s), which provide electrical connections between I/O pads on the bottom surface of the chip carrier substrate (102) and a footprint of corresponding pads on the surface of the organic substrate (104). In FIG. 1, the organic substrate (104) may comprise a PCB or PWB having other chips and electronic components mounted thereon, or it may be an organic carrier that may ultimately be mounted to a PWB. The chip carrier substrate (102) comprises electrical wiring patterns on the surfaces thereof which are connected by electrical through via contacts to thereby provide a space transformation of the electrical interface between the I/O pads on the chip (101) to the organic substrate (104).
Moreover, chip carrier substrate (102) is mechanically coupled to the organic substrate (104) using an underfill material (106) disposed between the chip carrier (102) and the organic substrate (104). The underfill material (106) (e.g., epoxy) is flowed into the interface between the chip carrier (102) and substrate (104) after formation of connections (105) and then cured to form a rigid material. The underfill material (106) acts to redistribute mechanical stresses in the interface between the carrier (102) and substrate (104) caused by relative displacement between the chip carrier (102) and organic substrate (104) due to CTE mismatch, to thereby minimize stress applied to the C4 connections (105). Underfilling ensures minimum load on the interconnects and becomes the primary load bearing member between the chip carrier (102) and the substrate (104) during thermal or power cycling. Thermoset type materials are commonly used in the industry as underfill material.
With the exemplary package structure (100) of FIG. 1, CTE mismatches between the chip (101), chip carrier (102) and organic substrate (104) can cause various types of defects over time as a result of thermal cycling, e.g., during temperature excursions, such as cool-down from underfill cure temperatures (150 C and higher) or normal power-on/off cycles. The most common defects include delaminations, fractures or severed electrical connections, and the probability that such defects will occur increases as the size of the package increases. FIG. 1 depicts a dotted line representing a “neutral stress point”, NSP, which is assumed to at the center of the chip package (100). The relative displacement due to the differences in thermal expansion between the chip (101), carrier substrate (102) and substrate (104) will be very small at the NSP, but will increase in accordance with the distance D (in all directions) from the NPS.
In the package structure of FIG. 1, when the chip and chip carrier are made of the same or similar materials such as silicon/silicon (Si CTE=2.8 ppm/C) or silicon/ceramic (ceramic CTE=˜9 ppm/C chip), there may be little stress in the interface between the chip (101) and the carrier (102) due to in-plane expansion. However, a significantly greater CTE mismatch between the chip carrier (102) and the organic substrate (104) (laminate CTE=12-18 ppm/C) and the high Young's modulus (>1 Mpsi) of the underfill (106) can combine to cause bending in the chip-laminate structure as well as large in-plane expansion of the carrier substrate (102) relative to the substrate (104).
Although the underfill material (106) compensates for the CTE mismatch between the chip carrier (102) and the substrate (104) and minimizes stress on the C4 connections (105), the underfill material (106) must be relatively rigid to bear much of the load. As a result the chip carrier (102) and substrate (104) are strongly coupled such that differential thermal expansion causes substantial bending or flexing upward or downward of the organic substrate (104) and chip carrier (102). In extreme cases, the bending can cause cracking of the chip carrier (102) or substrate, and delamination and contact damage in the interface between the chip carrier (102) and organic substrate (104). In addition, the bending of the chip carrier (102) can cause undue stresses and strains between the chip carrier (102) and chip (101) leading to defects and structural damage, etc.
In other conventional methods, a uniform stiffener can be attached to the organic substrate, where the CTE of the stiffener is chosen to match that of the substrate in order to eliminate bending. In particular, FIG. 2 is a schematic side-view illustration of another conventional package structure (200). The package (200) is similar to the package (100) discussed above, except that a high-CTE stiffener substrate (201) is attached to the bottom surface of the organic substrate (104). The stiffener substrate (201) significantly reduces the bending of the package structure (200) (as compared to the package structure (100) of FIG. 1), but does not offset (in fact, it enforces) a large in-plane expansion between the organic substrate (104) relative to the chip carrier (102). Consequently, excessive shear stresses can be applied to the C4s connections (105) between the chip carrier (102) and the organic substrate (104), as well as some local bending near the outer peripheral regions of the chip carrier (102).